1. Technical Field
The present invention relates to semiconductor devices in general, and in particular to a multilayer semiconductor device and a method for forming an interconnect structure within a multilayer semiconductor device. Still more particularly, the present invention relates to a multilayer semiconductor device and a method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device.
2. Description of the Prior Art
Within an integrated circuit (IC) device, various electrical components are formed on a semiconductor substrate. These electrical components are normally interconnected with metal lines that are typically formed by a combination of processes such as deposition, masking, and etching, commonly referred to as metalization.
Generally speaking, metalization begins at a masking area where small openings called vias are etched through all surface layers, down to the active regions of an IC device. Following a trench formation, a thin layer of conductive material is deposited by techniques such as vacuum evaporation, sputtering, or chemical vapor deposition (CVD). The unwanted portions of this layer of conductive material are then removed by a chemical-mechanical polishing (CMP) process. The CMP process leaves the surface layer covered with thin metal lines that are commonly known as interconnects.
A single-level interconnect structure such as the one described above is known as a single damascene structure. As chip density increases, a multi-level interconnect structure known as a dual damascene structure is generally more desirable. A multi-level interconnect structure typically begins with a standard metalization process that leaves the surface components partially wired together. Next, a layer of dielectric material such as an oxide, silicon nitride, or polyamide is deposited on the partially wired single damascene structure. Subsequently, a masking step that etches multiple vias down to a first level metal is performed on the dielectric layer to form a dual damascene structure.
Regardless of whether a single or dual damascene structure is being utilized, with the replacement of aluminum-alloy by copper as the source material for fabricating interconnects, the usage of a medium having a very low dielectric property (i.e., a dielectric constant of less than 2.5) to serve as a dielectric layer within the damascene structure is critical for the performance of IC devices. At one point, porous silica, such as aerogel or xerogel, was being considered by the semiconductor industry as a candidate for the dielectric medium because of its low dielectric constant. For example, bulk aerogel has a dielectric constant of approximately 1.0, and xerogel has a dielectric constant of approximately 1.7. However, despite its low dielectric constant, porous silica also has a very delicate, low density structure that possesses many microscopic voids. These microscopic voids make porous silica very fragile. In fact, porous silica is so fragile that a dielectric layer made of porous silica can easily be damaged by the CMP process utilized in conjunction with the damascene method of metalization.
Although alternative etching methods such as Subtractive Etching can be utilized instead of the CMP process for polishing a porous silica dielectric layer, these alternative etching methods are generally more arduous with copper interconnects due to the intrinsic difficulty of etching copper material. Furthermore, these alternative etching methods are typically more complex than the generally accepted damascene approach. Thus, the idea of utilizing porous silica as the dielectric layer within a damascene structure has not been proven practical in the semiconductor industry at large.
Consequently, it would be desirable to provide a method for composing an improved dielectric layer within an interconnect structure of a multilayer IC device. This improved dielectric layer is required to have a very low dielectric constant and should also be able to withstand damage from a standard CMP procedure.
In accordance with a method of the present invention, a layer of silica precursor material is first deposited on a silicon substrate. Without affecting its structure and porosity, the layer of silica precursor material is then dried; and the layer of silica precursor material becomes porous silica film. Subsequently, a protective layer, such as parylene, is deposited on top of the dried porous silica film. The thickness of the protective layer should be greater than the peak-valley planarization requirements of the silicon substrate surface. As a result, a composite porous silica film, which services as a dielectric layer within an interconnect structure, is formed. This composite porous silica film has a relatively low dielectric constant and is able to withstand damage from a standard CMP procedure.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.